Fully differential switched capacitor integrators generally include an input path including two sampling capacitors, a fully differential amplifier, two integration capacitors and eight switches. A typical example of a differential switched capacitor integrator made according to the known technique is illustrated in FIG. 1 wherein the sampling capacitors are, respectively, C.sub.s1 and C.sub.s2 both having a capacitance C.sub.s.
During a certain period of time which may be named phase-1, the clock generator V.sub.cl1 forces the switches S.sub.w1, S.sub.w2, S.sub.w3 and S.sub.w4 in the low resistance mode. Simultaneously the clock generator V.sub.cl2 forces the switches S.sub.w5, S.sub.w6, S.sub.w7 and S.sub.w8 into the high resistance mode. During such a period of time or phase-1, the sampling capacitors are charged to the input voltage and acquire an electric charge equal to: EQU 1/2.multidot.V.sub.i .multidot.C.sub.s
During the successive period of time named phase-2, the clock generator V.sub.cl1 forces the switches S.sub.w1, S.sub.w2, S.sub.w3 and S.sub.w4 into the high resistance mode and the clock generator V.sub.cl2 forces the switches S.sub.w5, S.sub.w6, S.sub.w7 and S.sub.w8 into the low resistance mode. The differential amplifier determines the transfer of charge from the sampling capacitor into the integration capacitors C.sub.i having a capacitance C.
Assuming that the charge transfer is complete, a z-transform expression representative of such a function is the following: EQU V.sub.o =V.sub.o .multidot.z.sup.-1 +V.sub.in .multidot.z.sup.-1 .multidot.C.sub.s /C
This expression is typical of a sampled data integrator having a time constant given by T.multidot.(C.sub.s /C);
wherein T is the time interval equal to the sum of the periods of time corresponding respectively to phase-1 and to phase-2.
Recourse to differential signal processing potentially reduces noise coupling from power supply rails, and increases the dynamic range. For reasons of fabrication technology, the integrator capacitor is always several times larger than the sampling capacitor, is built in practice connecting in parallel capacitors of unitary value equal to C.sub.s. The number n of capacitors connected in parallel is equal to the maximum integer smaller than C/C.sub.s. An additional capacitor of capacitance equal to: C-n.multidot.C.sub.s is also connected in parallel. This ensemble of capacitors is known as a capacitor array. In previous art configurations two arrays of unitary value capacitors are required for making a differential integrator.
On the other hand, in the majority of cases, it would be much more convenient and technologically more simple to be able to make a differential switched capacitor integrator requiring only a single array of capacitors that has a smaller total capacitance.